Integrated circuits utilize metal lines to provide conductivity within the circuit. Typically, memory arrays are constructed with a plurality of metal lines arranged in a number of columns and rows. The column lines are known as bitlines, and the rows lines are know as word lines. As process technology advances, the metal lines become smaller in their pitch (i.e. the distance between the metal lines is decreased). Although a smaller pitch for metal lines in an integrated circuit decreases the size of the circuit, such as the memory array, the decreased pitch introduces other problems. For example, for the memory array, the closer metal bitlines result in increased parasitic coupling between the bitlines. In order to reduce parasitic coupling between bitlines in such memory arrays, it is desirable to reduce the number of metal bitlines required in a memory array.
FIG. 1a illustrates a prior art static random access memory (SRAM) cell 100 utilizing a single bit line cross-point cell activation architecture. The memory cell 100 contains two cross-coupled inverters coupled to a single bitline 110 via n-channel metal oxide field effect transistors (MOSFETs) 112 and 114. The n-channel transistors 112 and 114 are controlled by an X address and a Y address. The memory cell 100 is constructed of two cross-coupled complimentary metal oxide semiconductor (CMOS) inverters 116 and 118 using a PMOS thin film transistor (TFT) as a load element.
The single bit line cross-point cell activation architecture uses a single bit line that is shared by a neighboring cell (not shown). Because of this, only three metal bitlines are required for two cells. However, because the memory cell 100 contains two stable points, one on each side of inverters 116 and 118, one of the stable points is reached for writing a high logic level to the input of inverter 116 by boosting the voltage of the X and Y wordlines above the operating voltage during the write cycle. A major disadvantage with the memory cell 100 configuration is that the bootstrapping technique, which requires generation of a voltage above the operating voltage, has negative ramifications. For a further explanation of the prior art memory cell 100, see IEEE International Solid State Circuits Conference, session 16, Static Memories, paper FA16.6, entitled, "A Single Bitline Cross-Point Cell Activation (SCPA) Architecture for Ultra Low Powered SRAMs," by Motomu Ukita, et al.
FIG. 1b illustrates a second prior art memory cell 120 that utilizes a single bitline architecture. In general, the SRAM cell 120 utilizes the full six transistor memory cell arrangement with thin film transistor (TFT) loads. Included in the six transistor memory cell are pass transistors 122 and 124. The pass transistors 122 and 124 couple both sides of the cell to a single bitline 126. The pass transistor 122 is controlled by an upper wordline 128, and the pass transistor 124 is controlled by a lower wordline 130. Therefore, the memory cell 120 requires separate control of the corresponding pass gates to pulse data into the cell.
Because the SRAM cell 120 is coupled to both the upper wordline 128 and the lower wordline 130 as shown in FIG. 1b, the scheme produces longer than required write pulse widths. Therefore, the prior art SRAM cell 120 sacrifices speed performance for the reduced bitline architecture. Although the memory cell 120 does not use the bootstrapping approach to write to both sides of the cell, a major disadvantage with this architecture is the longer write cycles and the use of six transistors for each cell. For a further explanation of the prior art SRAM cell 120, see the IEEE International Solid State Circuits Conference, 1993, session 16, Static Memories, paper FA 16.5, entitled, "A 16 Mb CMOS SRAM With a 2.3 Micrometer Single-Bit-Line Memory Cell," by Katsuro Sasaki, et al.